1. Field of the Invention
The present invention relates to integrated circuits, and in particular, to a circuit within an integrated circuit for detecting the test mode operation of the integrated circuit, and for preventing the integrated circuit from erroneously entering the test mode.
2. Description of the Prior Art
An integrated circuit (IC) may be tested at various stages during the production and use of the IC. For example, tests may be performed following production to verify that the IC exhibits functional and parametric characteristics that conform to the specification for the IC.
To facilitate testing, it is common practice in prior art ICs to add one or more input and output (I/O) pins to the IC specifically for receiving test signals generated by an automatic test equipment during the test mode. However, additional I/O pins undesirably increase the size of the IC which results in increased packaging costs.
To overcome the above-referenced drawbacks, other prior art ICs have included a test mode detection circuit 12 in the IC 1, as shown in FIG. 1. The IC 1 has a normal mode operating circuit 11 having an I/O pin which is originally designed for I/O functions during normal operation of the IC 1. This I/O pin is multiplexed to receive a test mode start-up signal which will in turn be identified by the test mode detection circuit 12. Thus, the arrangement shown in FIG. 1 detects the modes of operation of the IC 1 without requiring additional pins.
Multiplexing functional pins to be used both as test mode input terminals and as functional input terminals still carries inherent disadvantages. The most significant drawback is that it is not uncommon for the IC to erroneously enter the test mode during normal operation of the IC due to unexpected noise or the like existing during the normal operation, or due to the rare malfunction of one or more circuit elements.
For purposes of this disclosure, xe2x80x9cnormal operationxe2x80x9d shall mean the operation of the IC after it has been deployed for use in a particular system or circuit. xe2x80x9cNormal operationxe2x80x9d is contrasted with operation of the IC during production, when testing takes place. In light of the above-described drawback, it is desired that the test mode be entered only during production, and that safeguards are taken to prevent the IC from erroneously entering the test mode during normal operation of the IC.
Thus, there still remains a need for an IC which overcomes the drawbacks of the prior art ICs, and which prevents the IC from erroneously entering a test mode during normal operation of the IC.
It is therefore an object of the present invention to provide an IC which obviates the need for extra input and output test pins for performing test operations.
It is a further object of the present invention to provide an IC which utilizes functional pins to input test mode triggering signals.
It is yet another object of the present invention to provide an IC which detects a test mode using an internal test mode detection circuit.
It is still another object of the present invention to provide an IC which employs an internal test mode detection circuit to identify test mode triggering signals which are input through functional pins.
It is a further object of the present invention to prevent an IC from erroneously entering a test mode during normal operation.
In order to accomplish the objects of the present invention, there is provided an IC including a start test mode circuit for generating a test mode start-up signal to cause the IC to enter a test mode, and an automatic reset circuit responsive to the test mode start-up signal for preventing the IC from erroneously entering a test mode during normal operation.
In one embodiment according to the present invention, the automatic reset circuit has a negative edge transition detector responsive to a negative edge of the test mode start-up signal for producing a system start-up driving signal, and a system start-up timer for producing a first reset signal to reset the IC in response to the system start-up driving signal, with the first reset signal exhibiting a delay with respect to the system start-up driving signal.
In one embodiment according to the present invention, the start test mode circuit includes a test triggering signal input terminal for receiving a test triggering signal, a data input terminal for receiving test data signal, a memory for storing a test data pattern, a comparator coupled to the memory and the data input terminal for comparing the test data signal and the test data pattern to produce a comparison signal, a D-type flip flop having a D input and coupled to the comparator for receiving the comparison signal, and an AND gate coupled to the Q output of the flip flop for generating the test mode start-up signal. The flip flop reproduces the comparison signal at its Q output to be sent to the AND gate after a predetermined time period.
The IC according to the present invention further includes another AND gate which is responsive to the test triggering signal and an inversion of the test mode start-up signal for generating a second reset signal to reset the IC during normal operation of the integrated circuit.
The present invention also provides a method for preventing an IC from erroneously entering a test mode, in which the IC includes a start test mode circuit for generating a test mode start-up signal to cause the IC to enter a test mode. The method includes the steps of detecting a negative edge of the test mode start-up signal, producing a system start-up driving signal responsive to the negative edge of the test mode start-up signal, and generating a first reset signal to reset the IC in response to the system start-up driving signal to reset the IC.
In one embodiment according to the present invention, the method further includes the step of delaying the generation of the first reset signal for a predetermined time period with respect to the system start-up driving signal.
The method according to the present invention further includes the step of prestoring a test data pattern which is distinctive from data signals that are expected to be input during normal operation. Another step according to the present invention is generating the test mode start-up signal upon locating a match between a test data pattern prestored in a memory in the start test mode circuit and a series of data signals input into the start test mode circuit.